Invited Talk I 3-D Integration Technology and Future Trend

3-D integration technologies are discussed focusing on key technologies such as through-silicon via (TSV), metal microbump, wafer thinning, wafer bonding, wafer alignment and so forth. It is shown that 3-D LSI is suitable for low power operation since the interconnection length can be significantly reduced and the parallel processing can be effectively introduced. In addition, a future new 3-D integration technology and heterogeneous integration technology called a super-chip integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip integration. Possibilities for new system-on-a chip (SoC) and heterogeneous LSIs by 3D integration and super-chip integration such as 3-D stacked multicore processor using new shared memory with reconfigurable memory address, 3-D stacked dependable processor with self-test and selfrepair function, GPU stacked 3-D image sensor with extremely fast processing speed, ultra-low power 3D green LSI with energy scavenger devices operated by reusable energy, 3-D brain-machine interface (BMI) devices etc. are also discussed. Reliability and dependability are significantly important in these new 3-D LSIs. Then influences of 3-D chip stacking and wafer stacking on device characteristic and reliability are discussed referring to mechanical stress and Cu contamination induced by Cu-TSVs and metal microbumps. It is revealed that device characteristics are deteriorated by mechanical stress induced by TSVs and metal microbumps and Cu contamination. In addition, in order to improve the dependability of 3-D LSIs, it is very important to dynamically test 3-D circuits and self-repair circuit failures using built-in-self-test circuits. It is also important to embed redundancy circuits in 3-D LSIs to replace failure TSVs by good TSVs. Consequently, design for test (DfT) is very important in 3-D LSI design. Speaker’s Bio Mitsu Koyanagi was born in Hokkaido, Japan on February 4, 1947. He received the B.S. degree in electrical engineering from Muroran Institute of Technology, Japan in March, 1969 and the M.S. and Ph.D. degrees in electronic engineering from Tohoku University, Sendai, Japan, in March, 1971 and 1974, respectively. He joined the Central Research Laboratory, Hitachi Ltd. in April, 1974 where he worked on research and development of MOS memory device and process technology and invented a stacked capacitor DRAM memory cell which has been widely used in the DRAM production. Stacked