The Regularized FPGA Development Platform Verification Flow for Wireless Mobile SoC
نویسندگان
چکیده
In the development and commercialization phase of information technology products implemented as a system on a chip (SoC), field-programmable gate array (FPGA) based platform has been widely used as the logic function test methodology for basic or advanced features and mobile station emulator. In this situation, to define the uniform verification approach on FPGA development platform, we introduce a regularized verification flow. To evaluate its availability, we consider 3rd generation partnership project (3GPP)-series Release 7 high speed packet access (HSPA) specifications. Finally along with this regularized verification flow, we have fully evaluated our implemented physical/higher layer of HSPA.
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