Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems

We present areaand power-efficient pipeline 128and 128/64-point fast Fourier transform (FFT) processors for 8x8 multipleinput multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones. key words: pipeline FFT processor, MIMO-OFDM, VLSI architecture, IEEE 802.11ac