RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Contemporary hardware implementations of artificial neural networks face the burden excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured compute both multiply-accumulate (MAC) function (AF) operations. CORDIC-based uses linear trigonometric relationships realize MAC AF operations respectively. proposed design is synthesized verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation signed fixed-point 8-bit our design, shows 60% less area, latency, power product (ALP) improvement 38% in 27% dissipation, 15% latency with respect state-of-the-art design. Further, Monte-Carlo simulations process-variations device-mismatch are performed model evaluate expectations functions randomness dynamic variation. variation that worst-case mean $189.73\mu W$ 63% state-of-the-art.