Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology
نویسندگان
چکیده
منابع مشابه
Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology
ABSTRACT This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high efficient common drain circuit provide...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2014
ISSN: 0975-8887
DOI: 10.5120/17319-7431