Large Field-Size Elliptic Curve Processor for Area-Constrained Applications

This article has proposed an efficient area-optimized elliptic curve cryptographic processor architecture over GF(2409) and GF(2571). The employs Lopez-Dahab projective point arithmetic operations. To do this, a hybrid Karatsuba multiplier of 4-split polynomials is proposed. uses general traditional schoolbook multiplication approaches. Moreover, the resources are reused to implement modular squares addition chains Itoh-Tsujii algorithm for inverse computations. reuse reduces overall area requirements. implementation performed in Verilog (HDL). achieved results provided on Xilinx Virtex 7 device. In addition, performance design evaluated ASIC 65 nm process technology. Consequently, figure-of-merit constructed compare FPGA implementations. An exhaustive comparison existing designs literature shows that utilizes less area. Therefore, right choice area-constrained applications.