Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating
نویسندگان
چکیده
منابع مشابه
Design of a Low Power Low Voltage Full Adder
In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder. This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology...
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An Energy Efficient Feedthrough Logic (EE-FTL) is proposed in this paper to reduce the power consumption for low power applications. The EE-FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style ...
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This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based ...
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ژورنال
عنوان ژورنال: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
سال: 2014
ISSN: 2320-3765,2278-8875
DOI: 10.15662/ijareeie.2014.0312025