An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC nonbinary-weighted multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise incomplete (DAC) switching settling. To reduce total capacitance, all values of DAC were divided by 16, a parallel-series scheme was used implement these noninteger capacitors. prototype fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. maximal differential nonlinearity integral measured as -0.4/0.54 -0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. signal-to-noise-and-distortion ratio effective number bits 69.51 dB 11.25 bits, input frequency 500 kHz sampling rate MS/s. features 18.39-fJ/conversion-step Figure-of-Merit (FoM) at