AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element boost and keep consumption under certain limits for several application domains. However, steady increase of using many custom heterogeneous tiles leads an expansion design integration cost limited re-usability. The recent widespread open-source RISC-V ISA provides potential develop modular compute units that can be domains high reduction non-recurring engineering costs. motivation this work bring modularity adaptability features tile-based by increasing their flexibility realize different configurations less time In work, AGILER proposed as adaptive tile-base architecture based processors. consists adaptable multi-/single-core supports 32-/64-bit ISAs memory hierarchies. Inter-tile communication developed on a network-on-chip degree system scalability. run-time adaptation through internal reconfiguration manager dynamic partial over Xilinx FPGAs. Evaluation results demonstrate up 685 MOPS $8\times 32$ -bit 316 64$ bandwidth 7.4 GB/s. evaluated Virtex Ultrascale+ FPGA maximum 38.1 ms single tile.