A VLSI Systolic Array for SRIF (Square Root Information Filter)

Implementing the square-root information Kalman filter on a Jacobi-type systolic array

Several systolic Kalman lters have appeared in the literature, with often complex hardware constructs to accomodate the algorithmic `anomalies'. Here, we follow a di erent route by working the original information lter into a so-called `Jacobi-type' algorithm, which is much more regular and directly ts onto a common and general Jacobi-type systolic array. The e ciency of the resulting systolic ...

A fast VLSI systolic array for large modulus residue addition

The Residue number system (RNS) is inherently suited to high speed computations using custom tailored VLSI systems. In this paper, an algorithm for residue addition, based on a novel, 'non unique' number representation scheme, is implemented by a systolic array embedded in a VLSI chip. The pipelined cells are implemented, using a true single phase clock dynamic circuit structure, with computer ...

Score Evaluation Within the Extended Square-Root Information Filter

Unified VLSI systolic array design for LZ data compression

Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel–Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array...

A square root filter for real time multivariate regression

An algorithm is developed which makes it possible to perform multivariate regression in real time. The algorithm belongs into the class of square root filters and exhibits outstanding numerical characteristics, particularly in ill-conditioned problems. Because of these properties the algorithm is well suited for implementation in process computers and special digital devices operating with redu...