A Scalable Digit-Parallel Polynomial Multiplier Architecture for NIST-Standardized Binary Elliptic Curves

This work presents a scalable digit-parallel finite field polynomial multiplier architecture with digit size of 32 bits for NIST-standardized binary elliptic fields. First, dedicated is proposed each recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, having support all variants fields curves proposed. For performance investigation, we have compared architectures design. After this, the are most relevant state-of-the-art multipliers. All implemented in Verilog HDL using Vivado IDE tool. The implementation results reported on 28 nm Virtex-7 FPGA technology. multipliers utilize slices 1182 (for m=163), 1451 m=233), 1589 m=283), 2093 m=409) 3451 m=571). Moreover, our designs can operate at maximum frequency 500, 476, 465, 451 443 MHz. Similarly, supported fields, (i) utilizes 3753 slices, (ii) achieves 305 MHz clock frequency, (iii) takes 0.013 ?s one multiplication (iv) consumes 3.905 W power. more area-efficient than recent Consequently, comparison to state art reveal that well suited cryptographic applications.