A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

This paper presents a design of 48 GHz CMOS phase-locked loop (PLL) for 60 millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, fundamental PLL with quadrature clock generation scheme is proposed. Specifically, an implicit capacitive-bridged shunt peaking network, second order harmonic filtering technique realized in voltage control oscillator (VCO) to broaden bandpass response, thereby avoiding complex common-mode resonant tank calibration and improving phase noise performance. A robust current mode logic (CML) static divider topology adopted realize prescaler generate clock. With load biasing circuit, locking range high performance improved its reliability enhanced over PVT corners. To improve image suppression ratio transceiver, proposed verified. Fabricated 65 nm process, occupies core area 800 ?m × 950 ?m. Over 45.2 52.6 GHz, measured in-band better than ?90 dBc/Hz@100 KHz offset, jitter less 155 fs. Moreover, reference spur ?60 dBc/Hz.